Along with the increasing system design complexity, an electronic system level design method is suggested by the ITRS (International Technology Roadmap for Semiconductors) to improve the system performance. In this method, the transistor, the gate, and the register are upgraded to the transaction-level.
In a transaction-level model, the simulating efficiency is a challenge. Due to the increasing system design complexity, the researchers endeavor to create some inventive methods to improve the simulating efficiency.